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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:06:34 04/12/2011 
-- Design Name: 
-- Module Name:    stack - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity stack is
    Port ( clk_stk : in  STD_LOGIC;       
	        we      : in  STD_LOGIC;
			  e_stk   : in  STD_LOGIC;        
			  d_in    : in  STD_LOGIC_VECTOR (9 downto 0);
           a_in    : in  STD_LOGIC_VECTOR (2 downto 0);
			  a_out   : out  STD_LOGIC_VECTOR (2 downto 0);
           d_out   : out STD_LOGIC_VECTOR (9 downto 0));
end stack;

architecture RTL of stack is
	type stack is array (0 to 7) of std_logic_vector(9 downto 0);

	signal stk : stack;

	begin
		process (clk_stk, e_stk, we)
		begin
			if rising_edge (clk_stk) then
				if e_stk = '1' then							
					if we = '1' then -- escritura
						stk(conv_integer(a_in)) <= d_in;					
					else --lectura				
						d_out <= stk(conv_integer(a_in));
						a_out <= a_in;
					end if;
				end if;
			end if;
		end process;
end RTL;

